An Area-Efficient 8-Stage Out-Of-Order Risc-V Core with Integrated Floating Point for Embedded FPGA Platforms

Abstract

An eight-stage out-of-order superscalar RISC-V core with integrated single precision floating point is presented, targeted at embedded FPGA deployment where logic area is constrained but tolerance to long latency floating point operations is still desirable. Dynamic scheduling is realised through a renaming front end backed by a 256-entry physical register file and a 64-entry register alias table, an instruction window with broadcast-based wakeup, and a reorder buffer that retires instructions strictly in program order so that the architectural state remains precise. Four pipelined execution units (an integer ALU, a load-store unit, an IEEE-754 single precision floating point adder and a single precision floating point multiplier) share one common result bus rather than per-unit forwarding networks, which keeps the cost of the wakeup logic in proportion with the rest of the pipeline. The floating point datapaths are built in fabric logic from a 24-by-24-bit array so that the dedicated DSP slices remain available for user accelerators sharing the FPGA. The core is described in Verilog and synthesised for a Xilinx Artix-7. On a small set of synthetic kernels (SAXPY, an 8-tap FIR filter and a matrix multiply), execution completes in 1.7 to 2.1 times fewer cycles than a baseline obtained by removing the rename, instruction window and reorder buffer from the same RTL, while total on-chip power stays below 1 W.