Skip to content

Author

V. Betz

We have 2 of 217 papers

We haven’t gathered this author’s papers yet. Follow them and we’ll fetch their work.

Not the right person? Other researchers publish under this name.

Sep 2026

FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage

This work proposes Double-Duty, a logic block architecture that decouples LUTs and adder chains by augmenting four extra inputs of the logic element to bypass LUTs and directly drive the adders.

Xilai Dai, Junius Pun, Anthony Fei et al. · 0 citations
Jul 2026

VTR-LLM: Multi-Agent LLM Framework for Automated Debugging of FPGA CAD Flows

VTR-LLM is presented, a fully automated, multi-agent framework for diagnosing and resolving failures in the Verilog-to-Routing (VTR) CAD flow, and can resolve 95% of all failures fully automatically, with robust performance across error categories.

Mohamed A. Elgammal, Jamie Wu, Lynne Liu et al. · 0 citations

We use cookies to run the site and, with your consent, for analytics and to show ads. See our Cookie Policy.