Vasikarla Renuka, N. Bhavana, Bandla Sandhya

FPGA-Based High-Performance Multiply–Accumulate Unit Using a Radix-4 Modified Booth Multiplier and Error-Correctable Carry Look-Ahead Adder

Multiply–Accumulate (MAC) units dominate the arithmetic workload of digital signal processing, communication, image-processing, and machine-learning datapaths. Conventional MAC architectures often realize multiplication and accumulation as distinct hardware stages, typically combining an array multiplier with a ripple-...