FPGA-Based High-Performance Multiply–Accumulate Unit Using a Radix-4 Modified Booth Multiplier and Error-Correctable Carry Look-Ahead Adder

Abstract

Multiply–Accumulate (MAC) units dominate the arithmetic workload of digital signal processing, communication, image-processing, and machine-learning datapaths. Conventional MAC architectures often realize multiplication and accumulation as distinct hardware stages, typically combining an array multiplier with a ripple-carry or other carry-propagating adder. The supplied design study identifies the resulting partial-product count, carry propagation, resource overhead, and power consumption as major limitations. This paper presents an FPGA-oriented MAC architecture that replaces the conventional multiplier with a Radix-4 Modified Booth Multiplier (MBM) and performs accumulation using an Error-Correctable Carry Look-Ahead Adder (EC-CLA). Radix-4 Booth recoding compresses the multiplier representation into coefficients drawn from {0, ±Y, ±2Y}, reducing the number of partial products. The EC-CLA precomputes generate and propagate signals and supplements the carry network with redundant/parity-based error checking, while a data-storage stage retains accumulated results and enables feedback for repeated MAC operations. The design is described in Verilog HDL and evaluated in Xilinx Vivado targeting a Zynq-7000 device. Reported results for N=8, 16, and 32 show consistent reductions in resource usage, total on-chip power, and delay. For N=32, LUT utilization decreases from 1505 to 1323, total on-chip power from 103.437 µW to 81.64 µW, and total delay from 75.487 ns to 23.705 ns. These correspond to reductions of approximately 12.1%, 21.1%, and 68.6%, respectively. The results indicate that the proposed MBM–EC-CLA combination is a practical architecture for high-throughput arithmetic kernels where power, latency, and FPGA resource utilization must be jointly controlled.