Vivek Raju Kosigi

Design & FPGA Implementation of 32-Bit Risc-V Processor with MAC & Perceptron Accelerators

The paper describes the architecture, implementation, and testing of a lightweight 32-bit RISC-V processor equipped with a MAC and single-layer perceptron accelerators. In this work, a simple approach to integrate acceleration components using the classic five-stage pipeline structure (IF, ID, EX, MEM, WB) without any...