Design & FPGA Implementation of 32-Bit Risc-V Processor with MAC & Perceptron Accelerators
Abstract
The paper describes the architecture, implementation, and testing of a lightweight 32-bit RISC-V processor equipped with a MAC and single-layer perceptron accelerators. In this work, a simple approach to integrate acceleration components using the classic five-stage pipeline structure (IF, ID, EX, MEM, WB) without any change in the instruction set was proposed, resulting in minimal integration overhead. The architecture was implemented using synthesizable Verilog HDL, and the implementation was done using Xilinx Artix-7 FPGA board with Vivado tool for simulation, synthesis, implementation, and bitstream generation process. From the post-implementation results, it can be seen that timing closure was achieved with operating frequency of 100 MHz, worst negative slack (WNS) of +0.741 ns, and worst hold slack (WHS) of +0.148 ns. The system consumed 3.6% of logic utilization in terms of LUTs and 10% of DSP slice utilization; in addition, total power consumed on chip by the system was estimated to be 0.071 W. Hardware functional correctness was demonstrated using FPGA hardware execution where the result obtained by the system was observed using LED and LCD interface.