Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing and debugging low-level code. We present HINT, an executable hardware-intent intermediate representation layer between behavioral specifications or executable oracles and RTL. HINT makes RTL-relevant microarchitecture explicit, supports pre-RTL checking, and supplies explicit RTL-lowering obligations. We evaluate HINT using both a minimal single-agent flow and a full staged workflow. Across seven operator cases, the HINT-mediated route, with no post-synthesis QoR refinement, produces contract-compliant synthesizable RTL on 7/7 cases; Direct C2RTL and C2HLSC apply to five cases and succeed on 5/5 and 1/5, respectively. Under matched Design Compiler synthesis, HINT reduces area by 5.0\%--26.2\% relative to five manual RTL implementations and by 8.9\%--86.1\% relative to five accepted Direct C2RTL results. RealBench AES and SDC, together with a Vortex VPU synthesizing to 561.67k~$\mu\mathrm{m}^2$, further demonstrate specification-driven, protocol-rich, memory-rich, and hierarchical designs. In the controlled operator study, the HINT-mediated route shows better observed convergence and avoids the severe implementation-quality degradation seen in several direct-generation results.
Tairan Cheng, Yi Liu, Dongsheng Zuo et al.· 0 citations
Approximate logic synthesis (ALS) is a promising design paradigm for error-resilient applications. It can automatically generate circuits with optimized delay, area, and power at the cost of small errors. Existing methods mainly apply local approximate changes (LACs) to shorten critical paths or reduce area. However, given the large search space of LACs, they struggle to achieve a good trade-off between both objectives. This restricts the timing optimization potential of approximate circuits, particularly since area savings can be reinvested to enhance the drive strength of timing-critical gates. This paper leverages population-based search to explore LACs with positive timing influence in parallel. We develop two LAC search actions specialized in critical path shortening and area reduction, respectively. Guided by a recommender system aware of circuit topology and quality, individuals iteratively execute suitable LAC search actions and refine their explored LAC sets by conflict-free combinations, thus balancing reductions in critical path depth and area. Area savings are then reinvested to enhance the drive strength of timing-critical gates, enabling further timing improvement. Experimental results show that compared to a state-of-the-art area-driven method, our framework further reduces 20.3% critical path delay with comparable area savings, while being 7.9× faster.
Xiangfei Hu, Yuyang Ye, Chang Meng et al.· ACM Transactions on Design A...· 0 citations