Aug 2026· International Symposium on Low Power Electronics and Design· pp. 1-6· 0 citations· 9 references
Computer Science
TL;DR
This work demonstrates that an ACIM macro in 22nm FDSOI can leverage independent back-gate biasing (VBB) to improve device characteristics, such as transconductance, which enables a reduction in the operating voltage and power of peripheral circuits while simultaneously increasing operational speed.
Abstract
Analog computing-in-memory (ACIM) is a promising technology that performs computation on the bit lines to alleviate memory bottleneck, but the non-idealities at low operating voltages and high frequencies bottleneck overall energy efficiency (TOPS/W) and linearity. This work demonstrates that an ACIM macro in 22nm FDSOI can leverage independent back-gate biasing (VBB) to improve device characteristics, such as transconductance (gm), which enables a reduction in the operating voltage and power of peripheral circuits while simultaneously increasing operational speed. Circuit simulations show that targeted back-bias tuning reduces system RMSE by 50% (from 7% to 3.4%) or alternatively achieves a 20% increase in TOPS/W for VBB-optimized ACIM compared to unbiased operation. The study establishes the feasibility of utilizing back-gate biasing as a critical mechanism to achieve both high functional precision and high-speed operational flexibility in advanced FDSOI nodes.
SRAM-based computing-in-memory (SRAM-CIM) alleviates the memory-wall bottleneck of the von Neumann architecture, enabling energy-efficient AI edge computing. Current-domain CIM schemes suffer from degraded linearity at low supply voltages, whereas time-domain CIM schemes are highly sensitive to process, voltage, and te...
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