A Feedback-Enabled Restorable 10T FinFET SRAM for Low-Power and High-Speed Operation at 10 nm

Abstract

This paper proposes a feedback-enabled 10T FinFET based static random-access memory (SRAM) cell for low-power and high-speed operation in 10-nm technology node. With the scaling up of technology in SRAM, there are issues to consider with regards to power consumption, access delay, leakage, noise sensitivity, and reliable data retention. To overcome such problems, a proposal was put forward for a 10-transistor-based architecture with cross coupled storage nodes, dedicated access and read paths, and a feedback assisted restoration mechanism. The feedback path restores the internal storage nodes after temporary voltage disturbances, and the specific read path decreases direct interference with the stored data. The proposed cell is simulated on the circuit level using transient analysis with 10-nm predictive technology model from Synopsys HSPICE, and then compared to the 32-nm implementation. The following factors, such as hold, read, write and power consumption, access delay, power-delay product (PDP), leakage characteristics, static noise margin and data-restoration behaviour are taken into account during the evaluation. With the proposed 10-nm implementation, the write power and write delay are decreased by 39.25% and 10.10%, respectively, and the read power and read delay are decreased by 39.45% and 9.99%, respectively, compared to the 32-nm baseline. The PDP reductions for writing and reading are 45.40% and 45.53% respectively. Besides, there is about 36.75% and 36.84% reduction in leakage current and leakage power, respectively. The stability and restoration analysis also highlights the internal stability and restoration capability of the feedback mechanism in response to transient voltage disturbances. In summary, the proposed feedback-enabled 10T FinFET SRAM offers a good power-performance trade-off, fast access time, low leakage, stability and data restoring characteristic, which are desirable for embedded memory and energy-efficient computing applications.