CertiHybrid-B: A Lyapunov-Budget-Aware Quantized Neural Predictive Controller for Certification-Oriented RTOS–FPGA Co-Architectures
TL;DR
This paper presents CertiHybrid-B, an RTOS–FPGA co-architecture pairing a FreeRTOS-class host with a streaming FPGA datapath supporting both the projected timing feasibility and the control stability of the hard real-time controller path.
Abstract
Learned controllers are increasingly deployed inside hard real-time loops in automotive and industrial automation, where a safety case for the hard real-time controller path typically targets a zero-miss execution budget (with the standards-mandated WCET arguments). In this paper, we present CertiHybrid-B, an RTOS–FPGA co-architecture pairing a FreeRTOS-class host with a streaming FPGA datapath. This datapath executes a quantized neural forward pass, a hardware Lyapunov monitor, a Lyapunov-budget-aware controller-selector among a fast neural mode, a safety-filtered mode, and a robust LQR fallback, and an on-fabric safety filter that clips the neural action to a Lyapunov-decrease interval in the scalar-input case and to a heuristic per-channel relaxation in the multi-input case. Across cart-pole and quadrotor experiments with up to 100 seeds, we confirmed that CertiHybrid-B maintained a 0% deadline-miss rate and eliminated closed-loop divergence. In particular, it significantly reduced the tracking RMSE from 0.278 to 0.057 rad compared to the existing single-mode baseline, all within an ultra-low PL-internal datapath latency of 280–380 ns and under 12% resource utilization—reported as an analytical resource estimate cross-checked by an on-device ARM software-equivalent proxy rather than a post-route synthesis result—thereby supporting both the projected timing feasibility and the control stability of the hard real-time controller path.