Real-Time Super-Resolution for Drone Imagery: A Low-Power, Low-Precision Approach with Hardware Acceleration

Abstract

This paper presents a hardware–software co-design framework for real-time super-resolution (SR) of low-quality video on resource-constrained edge platforms. At its core is a compact residual network obtained by once-for-all (OFA) neural architecture search over the Residual Channel Attention Network (RCAN) design space, trained conventionally and then optimized with quantization-aware training (QAT) for deployment on an integer-only deep-learning processing unit (DPU). Loop tiling and data-flow scheduling are applied within a custom high-level synthesis (HLS) pre-processing pipeline that feeds the DPU, and a per-directive ablation isolates the contribution of each optimization to post-route resource usage and timing. Deployed on a Kria KV260 board with a 128×128 network input, the INT8 network sustains 96.37 FPS at the ×2 scale at a measured board power of 5.38 W, corresponding to 6.32 Mpixel/s of reconstructed output at 1.17 Mpixel/J, within 63.2% of the device LUT budget and with timing closed at 275 MHz. Relative to the FP32 model, INT8 quantization costs 0.274 dB of peak signal-to-noise ratio (PSNR) on Set5, 0.172 dB on Set14, 0.116 dB on B100, and 0.146 dB on Urban100, a loss dominated (81–90%) by activation rather than weight quantization. On a held-out UAV subset drawn from VisDrone2019, which is the operating domain the system targets, the network reconstructs at 25.94 dB and 0.748 SSIM. These results show that a twenty-three-layer residual SR network can be deployed within a 5.38 W envelope on a low-cost integer-only edge FPGA, making the approach suitable for autonomous systems, robotics, and airborne surveillance.