Fault Ride-Through Enhancement of a 9 MW DFIG Wind Farm Using a Dual-Layer STATCOM and Multi-Tier Protection Scheme: Detailed and Reduced-Order Modelling
Aug 2026· Wind· Vol 6, pp. 39· 0 citations· 63 references
Abstract
The doubly fed induction generator (DFIG) dominates the wind energy market, yet its direct stator-to-grid connection makes it vulnerable to grid faults, creating a tension between hardware self-protection and grid-code fault ride-through (FRT) compliance. This paper presents the modelling and FRT analysis of a 9 MW DFIG wind farm combining a 20 MVA Static Synchronous Compensator (STATCOM) with a ten-tier algorithmic protection scheme. A detailed phasor-domain MATLAB/Simulink R2024b model is complemented by physics-based reduced-order models integrated in Python, separating calibration targets, calibration-dependent derived quantities and quantities independent of the DC-link calibration. The aerodynamic model reproduces the power coefficient maximum of 0.48 at a tip–speed ratio of 8.1. The energy-balance model uses two parameters identified per scenario from the detailed DC-link trajectory; its peak-voltage agreement within 0.4% is therefore a calibrated consistency check, while the derived arming times, slopes, chopper sizing and latency budget remain conditional on that calibration. A first-order Thevenin analysis shows that the STATCOM supports a weak 25 kV point of common coupling of order 53 MVA short-circuit level, not the 2500 MVA source. The approximate 0.50-to-0.78 p.u. recovery requires about 29.7 Mvar and 1.90 p.u. of STATCOM rated current for 150 ms, conditional on an assumed short-time envelope and adequate converter-voltage headroom; it is not attributable to continuous rated operation. FRT support for the selected recoverable dip is separated from converter survival during a zero-impedance fault, for which a 1700 V chopper pickup with a 1 ms gate delay, not the 10 ms isolation command, is the clamping mechanism. The assessment is explicitly conditional and requires electromagnetic-transient and hardware-in-the-loop confirmation.
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