A Secure and High-Efficiency Packetized Test Network Architecture for Complex SoCs

Security IP for Pre-Boot CPU Initialization and Runtime Scenarios in Modern SoCs

Low-Overhead Power Side-Channel Resistant AES Accelerator for RISC-V via Stall-Induced Trace Desynchronization and Activity Equalization

The rapid proliferation of Internet-of-Things (IoT) applications has increased the demand for secure and efficient cryptographic processing in resource-constrained System-on-Chips (SoCs). This brief presents a compact and hardware-efficient Advanced Encryption Standard (AES) accelerator for RISC-V (RISCY) processors, i...

PipSORE: pipelined AES hardware design with shared one-round key expansion

PipSORE is introduced, a novel architectural optimization focused on area and power and the single- and multi-core PipSORE architectures are proposed and evaluated and utilize the outer-round pipelining technique.

A Secure Logic Locking Integration Technique for AES Algorithm

The results indicate that the proposed integration enhances SAT attack resistance while maintaining acceptable hardware overhead, making it suitable for secure IoT hardware deployments.

Lightweight Strategies for Reliability Improvement of PUF-Based Authentication in Resource-Constrained Devices

Cyberattacks represent a serious threat for the security of network-based systems and are responsible for large economic losses every year. In this context, physical unclonable function (PUF)-based authentication can provide access to the network resources to legitimate users only, thus preventing unauthorized accesses...

Design of (PUF) Physical Unclonable Function Using FPGA and Secured Clock Network (SCN)

A constant growth in the number of microelectronic devices and applications is accompanied by a constant rise in the need forgoods that are genuine and secure, as well as for electronic systems that are trustworthy. The security requirements for the vast majority of applications are quite stringent and continually evol...