A Secure Logic Locking Integration Technique for AES Algorithm

Abstract

The globalization of semiconductor manufacturing has increased vulnerabilities such as hardware Trojan insertion, overbuilding, reverse engineering, and intellectual property piracy. Logic locking has emerged as an effective countermeasure to protect integrated circuits using secret key activation. The Advanced Encryption Standard (AES) is widely deployed in Internet of Things (IoT) systems and therefore requires robust hardware-level protection. This work presents an architecture-level integration of Random Logic Locking and an Anti-SAT block within an AES encryption core implemented on an Artix-7 FPGA. Unlike prior studies that primarily evaluate Anti-SAT on benchmark circuits, the proposed approach embeds the locking framework directly into a complete cryptographic datapath and analyzes both hardware overhead and security characteristics. The design is evaluated in terms of area, power, throughput, Hamming distance corruptibility, and Satisfiability Checking(SAT) attack resilience. Experimental results demonstrate approximately 50\% output corruption under incorrect keys and incorrect key convergence during SAT attack attempts across multiple key sizes. The results indicate that the proposed integration enhances SAT attack resistance while maintaining acceptable hardware overhead, making it suitable for secure IoT hardware deployments.