An Area-Efficient Arbiter PUF Architecture for Secure Authentication in IoT Systems

Abstract

The widespread deployment of Internet of things (IoT) devices across diverse applications has increased the need for secure authentication in resource-constrained environments. Physical unclonable functions (PUFs) exploit intrinsic manufacturing variations to generate unique device responses without storing secret credentials. This work presents an area-efficient arbiter PUF design in 28 nm CMOS for IoT authentication. The proposed design is evaluated in terms of timing, area-delay trade-off, and power consumption. Compared to the conventional architecture, it exhibits higher propagation delay and increased per-stage delay contribution under equivalent conditions, reflecting an inherent area–delay trade-off. The design introduces a modest increase in transistor count per stage while maintaining comparable power characteristics. It achieves strong uniqueness (49.41%) and uniformity (49.97%), demonstrating stable statistical behavior. These results indicate suitability for hardware-based authentication in resource-constrained IoT systems.