Low-Power FPGA Implementation of Twin Support Vector Machine-Based Epileptic Seizure Detection Algorithm

Abstract

In neurological research, detecting epileptic seizures is the most crucial task using electroencephalogram (EEG) signals for clinical applications. Implementing a conventional support vector machine (SVM) for seizure detection is computationally intensive for real-time applications. The twin SVM (TSVM), a variant of SVM, along with the sequential minimal optimization (SMO) algorithm, is appropriate for hardware acceleration as it provides reduced computational complexity with better classification performance. In order to detect seizures in real-time using EEG signals, this article presents the field-programmable gate array (FPGA)-based implementation of the TSVM framework accelerated using the SMO algorithm for efficient real-time seizure detection on an Xilinx Virtex 7 FPGA board. The proposed framework follows a software–hardware (S/H) co-design methodology, in which EEG preprocessing, normalization, feature extraction, and feature selection are implemented in MATLAB, whereas the SMO optimization engine and TSVM classifier are implemented on FPGA hardware, thereby achieving better computation with minimal power consumption through efficient arithmetic operations and parallel processing. The proposed design is validated on benchmark EEG datasets from the CHB-MIT dataset, achieving high classification accuracy and low latency when implemented with a linear kernel TSVM. Besides that, it uses $1.6\times $ less power compared to the earlier performed implementation in prior work using SVM. A more accurate diagnosis through TSVM may lead to better treatment and patient care. The development of TSVM and SMO algorithms is expected to improve seizure detection and treatment. It will, in turn, allow for more efficient and effective medical solutions.