Network-on-Chip Technologies for High-Throughput and Low-Latency Communication

Abstract

With the growing demands of the performance of multi-core systems, conventional bus architectures have posed a challenge to in-chip communication due to its low-scaling nature and challenges of globally synchronizing clocks. The Network-on-Chip (NoC) is based on the principles of the modern communication network and it offers a basic solution to high-throughput and low-latency communications. This paper systematically reviews major NoC technologies to meet these demands. It first introduces the state of research currently in terms of topology, routing algorithms, and router microstructure. In the analysis module, critical drawbacks of traditional systems are revealed, such as unbalanced load in mesh structures, congestion issues with deterministic routing, and inefficient resource use in common router structures. Finally, this paper summarizes the trade-offs between power consumption, area and performance in the current technologies, and discusses the likely future trends including machine learning based intelligent routing and 3D integration. This paper aims to offer a technical reference systematically on the designs of highperformance NoC in the future.