Design and Analysis of Low Power CMOS Full Adders: A Comprehensive Review of Architectures, Logic Styles, and Performance Optimization

Abstract

The full adder (FA) remains the fundamental arithmetic building block in modern digital systems, serving as the critical component in arithmetic logic units (ALUs), multipliers, and digital signal processors (DSPs) . As CMOS technology continues scaling into the nanometer regime, power dissipation has emerged as the primary design constraint, driving extensive research into low-power full adder architectures. This review provides a comprehensive examination of CMOS full adder design methodologies, synthesizing findings from recent literature spanning 2010–2026. The review systematically analyzes logic style alternatives including conventional complementary CMOS, pass transistor logic (PTL), transmission gate logic, gate diffusion input (GDI), adiabatic logic, and emerging technologies such as FinFET and compute-in-memory (CiM) architectures . Performance metrics including power consumption, propagation delay, power-delay product (PDP), and transistor count are comparatively evaluated across design alternatives. Key findings reveal that hybrid approaches intelligently combining complementary logic styles consistently outperform single-style implementations, with GDI-based designs achieving significant transistor count reductions and FinFET-based adiabatic logic demonstrating power consumption as low as 4.36 nW at 14 nm technology . The review identifies critical trade-offs between power, speed, and area, and provides guidance for technology selection based on application requirements