An Enhanced CMOS Design for a High-Speed and Low-Power 4X16 Reversible Decoder

Abstract

In fields including low-power CMOS, DNA computing, quantum computing, photonic, and nanotechnology, among others, reversible logic circuit design is playing a significant role. These days, power dissipation and heat removal issues plague all electronic equipment. Reversible logic circuits can readily solve these issues. Decoders are the classified components that can decode addresses and instructions in any computing system. Reversible logic is widely used in VLSI design. The method presented in this study enables the designer to take advantage of reversible logic in their decoder circuits. Feed-back-Fan-out Under the constraints of logical reversibility, the combination is unacceptable. It is intended for use in a variety of fields, including high-performance computing, computer graphics, and nanoscale. The suggested design Consumes 13.07 nanowatts of power and incurs a 30-microsecond delay. This proposed method presents a reversible logic circuit in terms of energy usage. It is primarily crucial for reducing the requirement for power supplies. Several decoder circuits, including the 2-to-4, 3-to-8, and 4-to-16 decoders, have been produced by this technique. Cadence 45 nm GPDK was used to validate the suggested 4x16 decoder design.