4-Transistor IGZO Ternary Content Addressable Memory Enabling Large-Scale Array Integration for In-Memory Computing

Abstract

We report a 4-transistor (4T) Ternary Content Addressable Memory (TCAM) that significantly reduces the physical footprint by employing dual-gate IGZO transistors. High-density TCAMs are essential components for memory augmented neural networks and advanced computing systems; however, the large physical footprint remains a significant limitation in conventional designs. The proposed TCAM unit cell adopts a simplified structure, reducing the transistor count to four, which is substantially lower than previous SRAM-based (16T) and oxide semiconductor-based (6T) counterparts. Moreover, connecting the search line directly to the gate electrode effectively mitigates IR drop, enhancing the design’s suitability for large-scale memory applications. Experimental results validate the proposed design, demonstrating accurate Hamming distance computations (155.9 nA/bit), high endurance (<inline-formula> <tex-math notation="LaTeX">$\gt$ </tex-math></inline-formula><inline-formula> <tex-math notation="LaTeX">$10^{{10}}$ </tex-math></inline-formula> cycles), and fast operation with 350 ps search latency and 220 ns write time.