Design and ASIC Implementation of a Reconfigurable Hybrid Approximate MAC Architecture for Energy-Efficient Computing

Abstract

This work presents a suitable design as well as implementing a reconfigurable 32-bit Multiply-Accumulate (MAC) unit based on a hybrid approximate adder architecture aimed at energy-efficient VLSI applications. The proposed design partitions the adder into three segments according to bit significance: an 8-bit approximate adder for the least significant bits (LSB), a 16-bit carry select adder (CSLA) for the middle region, and an 8-bit Brent–Kung prefix adder for the most significant bits (MSB). This hybrid approach achieves a trade-off between computational accuracy and hardware efficiency by lowering complexity in non-critical regions while maintaining accuracy in critical paths. It operates in both reconfigurable and non-reconfigurable modes, and it can perform both accurate and approximate computations, which is a precious feature in error-tolerance-based applications like signal processing, machine learning etc. The logic of the proposed architectures has been designed through Verilog HDL and the correctness of the proposed technique has been established through the simulation. Physical design flow (from netlist to tape-out ready) is carried out in 14nm technology using SAED 14nm standard cell library at worst SS corner, 0.585V and 125°C temperature, using Synopsys ICC2 tool for placement, clock tree synthesis and routing. Various checks, such as Design Rule Check (DRC), Layout Versus Schematic (LVS) and formal equivalence checking, have been carried out for ensuring correctness of final layout. In summary, the proposed architecture achieves approximately a depletion of area with 14.36% and 22.47% cutdown in delay if comparison takes place with the exact MAC implementation while maintaining acceptable computational accuracy.