Real-Time FPGA Implementation of a Low-Complexity Time-Frequency Hybrid Equalization Architecture for DP-QPSK Coherent Reception in Datacenter Scale-Across Interconnects

Abstract

This work presents a real-time coherent receiving algorithm for 32Gbaud low-complexity DP-QPSK signals and deploys it on a single FPGA for datacenter scale-across interconnects. This real-time hardware algorithm, with a 5/4 samples per symbol (SPS) frequency-domain timing recovery algorithm (TR), a 1 SPS frequency-domain constant modulo blind equalization algorithm (CMA), and a 1 SPS time-domain carrier recovery algorithm (CR), significantly reduces the complexity of traditional frequency-domain equalization through methods such as DSP48E2 resources multiplex, DFT/IDFT modules multiplex, and Look-Up Tables (LUTs) resources multiplex. Moreover, it can further integrate IQ skew compensation (IQC) and chromatic dispersion compensation (CDC) without consuming additional resources. Finally, in a 40 km standard single-mode fiber (SSMF) optical transmission system without Erbium Doped Fiber Amplifier (EDFA), with a reception optical power of −30 dBm, it achieves a bit error rate (BER) performance of 7% hard-decision forward-error-correction (HD-FEC) threshold and a net rate of 119.62 Gbps, setting the current record for the highest net rate of single-carrier real-time coherent reception on a single FPGA.