Bridging the DSP Gap: A Streamed, Multiplier-Less Edge AI Operator via Logarithmic Co-Design

Abstract

Low-cost FPGA SoCs can be limited by DSP availability even when logic remains available. We present an edge-AI operator that co-designs selected-layer logarithmic quantization with a synthesizable shift-and-add datapath and AXI-compatible integration. Across classification, segmentation, and detection, short Log-QAT retains 99.79-99.94% of matched FP32 task quality. On a Zynq-7020, the 9-tap operator uses 0 DSPs and 358 LUTs, reaches 205.04 MHz, and delivers 2.2996 GOPS/W. Relative to matched DSP-MAC and LUT-multiplier baselines, it improves post-route frequency and energy efficiency while remaining DSP-free. Pynq-Z2 experiments reproduce the expected raw outputs in all 40 board cases. These results establish a reusable, physically validated zero-DSP operator and an initial streamed deployment path without claiming a task-complete accelerator.