Transconductance ZTC Bias Study under High Temperatures: Experimental and Analytical Model

Abstract

This contribution redefines biasing strategies for thermally-tolerant design of analog Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) by demonstrating that transconductance (gm) zero-temperaturecoefficient $\left(\boldsymbol{Z} T C_{\boldsymbol{g} \boldsymbol{m}}\right)$ operation provides intrinsic stability of key electrical performance metrics under high-temperature (T) conditions. A compact analytical model is proposed to predict the $\boldsymbol{Z} \boldsymbol{T}_{\boldsymbol{g} \boldsymbol{m}}$ bias voltage $\left(\boldsymbol{V}_{\boldsymbol{g} \boldsymbol{m} \boldsymbol{Z} \boldsymbol{T} \boldsymbol{c}}\right)$ with high accuracy ($\boldsymbol{\leq} \mathbf{2. 1 7 \%}$ error) over a wide $\boldsymbol{T}$-range (300-500 K), offering a practical alternative to involved existing formulations. Experimental validation across conventional (RM) and advanced Diamond (DM) and Half-Diamond (HDM) MOSFET layouts reveals that the $\boldsymbol{Z} \boldsymbol{T}_{\boldsymbol{g} \boldsymbol{m}}$ bias condition is layout-invariant, while enabling substantial electrical performance gains, with up to 70.43% enhancement in normalized gm. In contrast, ZTC ${ }_{\text {IDS }}$ bias point for a $\boldsymbol{T}$-invariant drain current $\left(\boldsymbol{I}_{\boldsymbol{D} \boldsymbol{S}}\right)$ is shown to degrade $\boldsymbol{g} \boldsymbol{m}$ by around 30% with T, compromising analog performance. These findings establish $\boldsymbol{Z T C}_{\boldsymbol{g} \boldsymbol{m}}$ biasing as a superior and scalable approach for high- $\boldsymbol{T}$ mixed-signal CMOS ICs, bridging devicelevel innovation and circuit-level reliability.