Area–Delay–Power Efficient FPGA Architecture for Real-Time Impulse Noise Removal Using Decision-Based Multiplexers and Adaptive Neighborhood Median Filtering

Abstract

Real-time image denoising requires a filtering architecture that simultaneously preserves image structure and satisfies strict hardware constraints on area, latency, and power. This paper presents an FPGA-oriented real-time impulse noise removal (RTINR) architecture built around a decision-based multiplexer and an adaptive-neighborhood median-selection network. The decision-based multiplexer compares two 8-bit pixel values and directly produces high and low outputs through comparator-controlled 2:1 multiplexers. These primitive cells are organized into multi-level adaptive-neighborhood blocks so that the median of a 3×3 processing window can be obtained without a conventional full sorting network. The architecture was modeled in Verilog HDL, simulated and synthesized using Xilinx ISE, while image-level denoising quality was assessed in MATLAB R2020a. Reported synthesis results show 437 slice LUTs, a total path delay of 20.375 ns, and on-chip power consumption of 32.83 mW. For the evaluated image case, the method achieves 54.53 dB PSNR and 0.992 SSIM. Relative to the compared standard, decision, and adaptive median filters, the RTINR architecture reduces LUT count, delay, and power while improving image-quality measures. The results indicate that comparator/multiplexer-centric median selection is a practical design strategy for low-resource, real-time FPGA image preprocessing in embedded vision systems