Energy-efficient approximate multipliers and adders for multimedia computing applications: Design and evaluation of novel optimized arithmetic circuits with enhanced accuracy

Abstract

Advanced electronics have become an integral part of human life, from smartphones in our pockets to modern vehicles on the road to satellites orbiting the Earth. Power consumption has become a major constraint in these applications. Approximate computing (AC) has emerged as one of the most promising paradigms and is pervasive across a wide range of error-resilient applications. Optimizing adders and multipliers is vital for energy- and area-efficient multimedia systems. AC is well-suited for arithmetic circuits. However, the increased hardware complexity of existing designs leads to higher area and power overheads. This article proposes high-performance simplified approximate adders through logic-level reduction. Novel-energy and area-efficient approximate multipliers are presented. Extensive design and accuracy metric analyses are performed using the Cadence Genus Synthesis Solution at the 45 nm technology node. The proposed designs achieve significant improvements in power, delay and area. Moreover, the Mean Error Distance, Normalized Mean Error Distance, and Mean Squared Error results demonstrate enhanced error characteristics compared with existing designs. The efficiency of the proposed designs is further demonstrated through their application in image smoothing and compression, with minimal impact on image quality.