Design of Error Efficient Inaccurate 3:2 Compressor for Approximate 8×8 Multiplier
TL;DR
Experimental results indicate that the proposed multiplier provides favorable accuracy–efficiency trade-offs and application-level validation using image multiplication and image convolution further demonstrates improved perceptual quality measured through PSNR and SSIM.
Abstract
Energy-efficient arithmetic units are critical for modern error-resilient computing systems. This work introduces a novel inaccurate 3:2 compressor that exploits input probability characteristics to reduce complexity by allowing a single, low probability error condition. The proposed approximation alters only the sum output for the all-one input combination, while maintaining an exact carry output. The compressor is integrated into a radix-4 methodology based 8×8 multiplier realized through a hierarchical composition of 2×2 and 4×4 multiplier modules. Three alternative architectures are developed for intermediate partial product accumulation using the proposed inexact 3:2 compressor. Error behavior is analyzed in MATLAB and benchmarked against existing inaccurate designs using Error Rate (ER), Mean Error Distance (MED), and Normalized Mean Error Distance (NMED). Hardware implementations are carried out in Cadence Spectre with GPDK 45-nm technology to evaluate area, power consumption, and delay. Experimental results indicate that the proposed multiplier provides favorable accuracy–efficiency trade-offs. Application-level validation using image multiplication and image convolution further demonstrates improved perceptual quality measured through PSNR and SSIM.