Lightweight Bit Manipulation Extension Architecture and Performance Evaluation for RISC-V Processors Based on the NICE Interface

Abstract

The open and modular RISC V instruction set architecture supports flexible domain specific extensions. However, conventional embedded RISC V processors rely on general purpose instruction sequences to implement bit manipulation operations, which suffer from long execution cycles, low computational efficiency, and high power consumption. To address these bottlenecks, this paper proposes a lightweight custom bit manipulation acceleration scheme based on the Nuclei E603 processor and the NICE (Nuclei Instruction Co-unit Extension) interface. We design six bit manipulation instructions functionally equivalent to the RISC V Zbb/Zbs standard extensions, define their instruction formats, perform instruction level functional simulation and verification, and implement corresponding software adaptation and optimization. Evaluation results on CoreMark and Dhrystone benchmarks show that the proposed scheme improves CoreMark performance by 3.37% and Dhrystone performance by 0.88%. The design features non-intrusiveness, lightweight design, low overhead, and high compatibility, making it well suited for low power embedded and edge computing applications.