PWM-induced lifetime enhancement in commercial 4H-SiC MOSFET gate oxides and the associated physical mechanisms of interface traps

Abstract

Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors are increasingly operated under high-frequency pulse-width-modulated (PWM) gate drive, yet gate-oxide reliability is still qualified almost exclusively under direct-current (DC) stress. This work reports a controlled comparison of gate-oxide time-dependent dielectric breakdown (TDDB) under DC and pulsed-voltage stress for three commercial 1.2 kV device families (Wolfspeed C2M and C3M planar, Infineon trench), and interprets the observed frequency dependence in terms of interface-trap dynamics. Pulsed-voltage TDDB measurements at 150 °C and five switching frequencies (DC to 100 kHz) show that the Weibull characteristic lifetime increases monotonically with frequency, with the 100 kHz value approximately four times the DC value (4.1×–4.7× across the three families). Trap time-constant spectroscopy based on the differential threshold-voltage method resolves a continuous, bimodal interface-trap spectrum g(τ), comprising a fast interface-state cluster near τ ≈0.7 ms and a slow near-interface-oxide-trap shoulder extending from about 0.5 to 50 s. The reduction of quasi-permanent threshold-voltage drift under millisecond pulsing (≈30% relative to DC at 150 °C) provides direct evidence that fast traps de-trap during each OFF interval, which is the proposed physical origin of the lifetime extension. An empirical correlation between the slow-trap filling-rate ratio derived from g(τ) and the measured lifetime ratio is examined; the two quantities agree within the propagated measurement uncertainty, but the relation is bounding and empirical, and the field mismatch between spectroscopy and TDDB testing is discussed explicitly. Series-resistance correction for TO-247 packages and a static scattering-balance descriptor (the phonon-to-Coulomb mobility ratio) are reported as supporting characterization. The results indicate that conventional DC qualification underestimates the gate-oxide lifetime available under realistic PWM operation and that the time constant of the interface trap and the frequency dependence have a certain correlation.