Microscopic Stress Analysis of Silicon Carbide Devices Under Overcurrent Conditions in DC Solid‐State Circuit Breakers

Abstract

During load start‐up, capacitor charging, pulsed‐power output and inverse‐time protection delay in dc solid‐state circuit breakers (DC‐SSCBs), SiC MOSFETs are subjected to short‐duration overcurrent (OC) stress. Ultrahigh gate voltage (UHGV) driving can reduce thermo‐mechanical stress during OC operation. However, the gate oxide of SiC MOSFETs has relatively limited reliability margins, and UHGV driving may introduce additional gate oxide reliability risks. Moreover, the internal microscopic stresses of the device cannot be directly characterised from external macroscopic electrothermal parameters. To address this issue, this paper establishes a combined system‐level Saber model and device‐level TCAD simulation methodology to analyse the external electrothermal responses and internal microscopic stress distributions of a SiC MOSFET under three operating conditions. The results show that OC operation at the nominal gate voltage significantly increases the current density, lattice temperature and thermo‐mechanical stress of the device. UHGV driving reduces on‐state loss, junction temperature and mechanical stress; nevertheless, it also enhances the local electric field in the trench gate oxide and carrier transport at the SiC/SiO 2 interface, thereby reducing the gate oxide reliability margin. The results provide guidance for OC gate‐drive design and reliability assessment of SiC MOSFETs in DC‐SSCBs.