Design and Implementation of a Low-Power 16-Bit MAC Unit using CEBEC SQRT CSLA

Abstract

Multiply-Accumulate (MAC) units are fundamental hardware blocks in Digital Signal Processing (DSP) systems, where dynamic power efficiency is a critical design constraint. Traditional high-speed MAC architectures frequently employ Square Root Carry Select Adders (SQRT CSLA) for the accumulation stage. However, regular SQRT CSLAs rely on redundant Ripple Carry Adders (RCAs) to compute parallel potential sums for both $\mathbf{C}_{\mathbf{i n}}=\mathbf{0}$ and $\mathbf{C}_{\mathbf{i n}}=\mathbf{1}$ conditions, leading to excessive dynamic switching activity. This paper proposes a highly power-efficient 16-bit MAC architecture utilizing a Carry Enable Binary to Excess-1 Converter (CEBEC) SQRT CSLA. The proposed design entirely eliminates the redundant $\mathbf{C}_{\text {in }} \boldsymbol{=} \mathbf{1}$ RCA blocks, replacing them with a streamlined combinational logic path. This path utilizes optimized NOT and XOR gates for lower-order bits, coupled with targeted OR-gate logic at the Most Significant Bit (MSB) for rapid carry evaluation. The baseline and proposed architectures were functionally verified via Cadence SimVision and synthesized to the gate level using the Cadence Genus Synthesis Solution. Post-synthesis power and area analysis demonstrates that the proposed CEBEC-based MAC unit achieves a significant 36.7% reduction in dynamic switching power compared to the baseline CSLA, dropping from 15.22 $\boldsymbol{\mu} \mathbf{W}$ to $\mathbf{9. 6 3} \boldsymbol{\mu} \mathbf{W}$. While this hardware optimization trades a marginal 5.3% increase in total standard cell area, the substantial mitigation of switching activity makes the proposed architecture highly viable for low-power DSP ASICs.