High Performance Fault-Resilient MAC Architecture for Mission-Critical AI Hardware
Abstract
Multiply Accumulate (MAC) units play an important role in high-performance AI/ML and digital signal processing systems where both reliability and computational efficiency are critical for achieving optimal performance. In this work, an optimized MAC unit is designed and implemented by integrating a Wallace Tree Multiplier to enable high speed multiplication and a Kogge-Stone adder to achieve low latency accumulation. The proposed architecture which is implemented in 90 nm technology is analyzed and compared with existing MAC designs in terms of performance, power consumption and area. The results show that the proposed architecture has a delay of 3.99 ns, power consumption of 0.507404 mW and an area of $2967.805 \mu \mathrm{m}^{2}$. To further improve the reliability of the design, a Triple Modular Redundancy (TMR) mechanism is incorporated which provides protection against both transient and permanent hardware faults. The simulation result verifies the implemented TMR mechanism in the proposed MAC architecture by operating correctly even when faults are present. A balanced trade off is achieved between speed, power efficiency and fault tolerance using the proposed MAC architecture which makes it ideal for high performance AI/ML applications.