A Low-Power 4-Bit Vedic Multiplier Utilizing Modified Gdi and Sapon Techniques

Abstract

In Digital Signal Processing (DSP) and other computational applications, the multiplier is a fundamental building block and efficient design of the multiplier has a significant impact in the enhancement of the performance of Integrated Circuits (ICs). Vedic Multipliers are one of the different types of multiplier architectures which are inspired from ancient Indian mathematics and are characterized by their parallel processing capability and high-speed performance. The multiplication in these architectures is modeled using parallel computation technique and this can enhance the operational efficiency. The paper describes the detailed analysis and evaluation of 4-bit Vedic multiplier designs based on Modified Gate Diffusion Input (MGDI) and Complementary Metal-Oxide-Semiconductor (CMOS) logic styles. In addition, the Carry Skip Adder (CSA) architecture is used to study its influence on the overall multiplier performance. The main goal of this work is to compare and analyze these multiplier designs based on delay, area and power characteristics among various logic families and adder structures. Transistor Count, Propagation Delay, Power Dissipation, Silicon Area and Power-Delay Product (PDP) are used for performance evaluation. The results obtained shows that the implementation using MGDI has achieved considerable results in terms of delay, area efficiency, power consumption and PDP compared to CMOS and Transmission Gate (TG) implementations. All the Vedic multiplier architectures are designed and implemented in 4-bit configuration using 45 nm technology and Tanner EDA Tools.