EVALUATING THE EFFECTIVENESS OF ALGORITHMIC NOISE REDUCTION IN POWER SIDE-CHANNEL ATTACKS ON AN FPGA-BASED CGRA CRYPTOGRAPHIC ACCELERATOR SUPPORTING MULTI-TASK AES-128

Abstract

Power side-channel attacks represent a serious threat to cryptographic accelerators implemented in hardware. This article experimentally evaluates the power side-channel vulnerability of LiCryptor, a CGRA-based cryptographic accelerator, when executing AES-128 in a pipelined, multi-threaded configuration supporting 16 concurrent tasks. The study considers a worst-case side-channel adversarial model in which the attacker has control over the input data. Based on the analysis of Hamming Weight and Hamming Distance leakage models, this article proposes a new algorithmic noise-reduction technique that fixes the input data of non-targeted tasks, thereby reducing superimposed leakage components unrelated to the target key. Experiments conducted on a Sakura-X FPGA board with 200K power traces show that the proposed technique increases the average SNR within the region of interest by approximately 8.5 times. For CPA, the number of attack models capable of fully recovering the key increases from 3/8 to 6/8, while the best-case MTD decreases from 82.1K to 20K traces. For profiled DL-SCA, evaluation using the Ranking Loss (RkL) function showed that the full-key Log2(KR) decreased from 102.9 to 47.0, while the number of successfully recovered key bytes increased from 1/16 to 8/16. These results indicate that algorithmic noise in multi-task architectures should not be regarded as a reliable protection mechanism against SCA, thereby underscoring the need to integrate dedicated SCA countermeasures from the early stages of cryptographic hardware design.