A Reconfigurable 11T SRAM Compute-in-Memory Architecture for Dual-Mode MAC Operations

Abstract

Current trends in hardware design for artificial intelligence and machine learning algorithms impose limits on traditional Von Neumann architectures due to the memory wall problem. Hence, researchers are focusing on versatile memory design and in-memory computing (IMC) architectures. The standard 6T SRAM cell is small and dense, but it suffers from read-disturb errors and variable switching speeds. These problems make it unreliable for massive parallel computation. There are benefits t ou sing t he c urrent 8 T a nd $8+$ T SRAM cell variants, but each has its pros and cons. For instance, the 8T design can handle vector operations but not internal accumulation, whereas the $8+T$ design offers strong buffering but can only perform local pairwise processing. To overcome these limitations, this paper proposes a reconfigurable 11T SRAM cell optimized for dual-mode MAC operations. The cell, with an area of $\mathbf{3 9. 6 7} \mu \mathrm{m}^{2}$, features an isolated read path to ensure data retention and a dedicated input interface that enables simultaneous computation on external inputs and stored weights. Using this bitcell, a $4 \times 4$ IMC array implemented in Cadence Virtuoso using SCL180 nm PDK, demonstrating correct end-to-end execution of MAC operations. Post-layout simulations of the 4×4 macro confirm a system-level MAC latency of 2 clock cycles with a total architecture footprint of $\mathbf{3 2, 1 6 1} \mu \mathbf{m}^{2}$, throughput of 278.40 GOPS, and energy consumption of 5.380 pJ. The physical scalability of a $4 \times 4$ array architecture confirms that the proposed design can perform hardware-accelerating functions within highly dense memory macros.