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Author

Pinalkumar J. Engineer

2 papers indexed here

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Aug 2026

A Reconfigurable 11T SRAM Compute-in-Memory Architecture for Dual-Mode MAC Operations

Current trends in hardware design for artificial intelligence and machine learning algorithms impose limits on traditional Von Neumann architectures due to the memory wall problem. Hence, researchers are focusing on versatile memory design and in-memory computing (IMC) architectures. The standard 6T SRAM cell is small...

Umang Mahendrabhai Joshi, Priyankkumar H. Prajapati, Pinalkumar J. Engineer et al. · 0 citations
Aug 2026

Energy and Area-Efficient Custom RISC-V ISA Extensions Using Hybrid 16-Bit Signed Multipliers on FPGAs

This work presents the design and integration of a hybrid 16-bit signed multiplier as a custom (X) instruction set architecture (ISA) extension within a five-stage pipelined RISC-V processor. The proposed RV32IX architecture is synthesized and implemented for the Zynq all programmable system-onchip (APSoC) FPGA platfor...

M. Nagar, Aditya Mathuriya, Sohan H. Patel et al. · 0 citations

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