Multi-Operand In-Memory Computation Using Quad-Read 12T SRAM

Abstract

In-memory computing (IMC) has emerged as a viable paradigm to overcome the limitations of the Von Neumann bottleneck, which limits frequent data transfer between memory and the CPU. Enabling two-operand Boolean and arithmetic operations within the SRAM array gives efficient data computing while multi-operand computation incur higher power and latency, revealing the limitation of IMC architectures. This work proposes a 12T SRAM cell with three wordlines and four bitlines for computing multi-operand operations to overcome this restriction. This iIMC approach with separate read/write SRAM concentrates on an extensive review of selecting an efficient SRAM based on it so perational principles, stability during evaluation, and power performance. Introducing a multi-logic sense amplifier reduces the latency of performing the XOR operation. The multi-operand IMC performs 8-bit three input XOR with throughput of 10.8 GOPS and operating efficiency of 4596 TOPS/W and four input XOR with throughput of 20.8 GOPS and operating efficiency of 8851 TOPS/Wat 1V which verified through continuous evaluation and variation in PVT.