Aug 2026· Engineering Research Express· Vol 8, pp. 175405· 0 citations· 41 references
Physics
TL;DR
This paper proposes ultra-lightweight topology MambaNeck, a hybrid detection architecture optimized for low-power edge systems, embedding a 1D selective state space model (SSM) within the feature fusion stage, and demonstrates that this logic-constrained designfundamentally minimizes required multiply-accumulate operations and off-chip memory access costs.
Abstract
Automated visual inspection of industrial surfaces demands a critical balance between accurate defect detection and the processing limits of field hardware. Traditional convolutional networks often miss elongated surface anomalies due to their restricted receptive fields, whereas transformer-based alternatives require excessive computational resources. To address these deployment bottlenecks, this paper proposes ultra-lightweight topology MambaNeck, a hybrid detection architecture optimized for low-power edge systems. By embedding a 1D selective state space model (SSM) within the feature fusion stage, the proposed method captures global defect characteristics at a linear computational cost, avoiding the optimization issues common in 2D scanning. Furthermore, an adaptive lightweight detection head (LiteShiftHead_AR) significantly reduces the arithmetic footprint. To ensure precise defect localization across highly variable defect sizes, we developed an Inner-Distance Intersection over Union loss. Crucially, cross-domain ablation studies confirm that its scale-prior thresholding exhibits remarkable robustness across diverse manufacturing datasets, effectively guiding boundary regression without adding inference latency. Evaluating the memory bandwidth bottlenecks of current SSMs, we quantitatively demonstrate that this logic-constrained design—operating at only 5.9 GFLOPs—fundamentally minimizes required multiply-accumulate (MAC) operations and off-chip memory access costs. Rather than providing an immediate deployment solution, our model serves as a theoretically efficient architectural baseline for custom hardware (e.g. FPGA/ASIC). Tests on the BDD-640 bearing dataset demonstrate that the model maintains robust localization precision, achieving 69.5% under the stringent mAP50-95 metric. Importantly, our experiments reveal a crucial dependence on initial weight distributions, indicating that robust pre-training is a necessary practical condition for deploying state-space visual inspection tools in data-scarce manufacturing scenarios.
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