The results demonstrate the effectiveness of the proposed framework for high-throughput wafer-defect inspection on desktop-class hardware, and its low parameter count makes it a promising candidate for future deployment on resource-constrained edge devices.
Abstract
In semiconductor manufacturing, automated wafer defect detection is critical for ensuring chip yield and process stability. In seismically active regions, sub-millimeter conveyor micro-displacements during seismic events can produce complex geometric anomalies on wafer surfaces, and the resulting need for rapid post-event inspection motivates the present work. Conventional convolutional neural networks (CNNs) face inherent limitations in capturing global spatial context and suffer from computational redundancy when processing micro-scale, multi-morphological defects. To address these challenges, this study proposes an improved YOLOv11 framework integrating three enhancements: an attention-based intra-scale feature interaction (AIFI) module at the backbone–neck interface to strengthen global semantic correlations, a lightweight asymmetric detection head (LADH) to decouple classification and localization tasks, and a geometry-aware SIoU loss to constrain bounding box regression from angular, distance, and shape perspectives. Experiments on a public benchmark of industrial wafer maps demonstrate that the proposed method improves mAP50 from 93.0% to 94.5% while maintaining 181.7 FPS on a desktop-class GPU. These results demonstrate the effectiveness of the proposed framework for high-throughput wafer-defect inspection on desktop-class hardware, and its low parameter count makes it a promising candidate for future deployment on resource-constrained edge devices.
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