Device-physics design rules for wide-temperature enhancement-mode GaN integrated circuits: code and circuit-level results

Abstract

Code and circuit-level results for the article "Device-physics design rules for wide-temperature enhancement-mode gallium nitride integrated circuits, revealed by transistor-anchored machine learning" (T. M. Mahim, M. M. Rahman, N. Chowdhury; submitted). The probe circuit is a monolithic e-mode GaN-on-SOI fractional-N phase-locked loop in which every block is built from e-mode HEMTs, sized by learned models (physics-informed neural network varactor model, differentiable loop model with adjoint gradients, reinforcement-learning feasibility test) and verified by transistor-level simulation with the foundry device model at ten temperatures from 218 to 423 K (ngspice with OpenVAF, cross-checked in VACASK). All results are simulations; no chip was fabricated. The foundry process design kit is covered by a non-disclosure agreement. This archive contains no PDK file and no data that transcribe PDK device parameters or device-level characteristics; holders of the kit can regenerate the private files with the included scripts (see README). Version 1.0.1: presentation changes only (two figures redrawn so that no label is clipped or overlaps the data, and two table texts reworded); no simulation result or number changed. See CHANGELOG.md.