The Reciprocal tau-Cell: A Log-Domain Circuit for On-Chip Learning
TL;DR
Transistor-level SKY130 simulations show that the second run gives the gradient within 1.9%; that hardware linearisation permits large, noise-robust error signals; that a 13-cell network learns the Iris data set; and that learning in situ restores mismatched circuits on which software-trained weights fail, from 53-63% to 88-96% test accuracy.
Abstract
Training hardware by gradient descent requires a gradient to be computed using a separate backwards pass. If a circuit is reciprocal, meaning every connection is symmetric, the backward pass is the same network run a second time with the error as its input. The reciprocal tau-cell, a weak-inversion log-domain circuit, makes this practical in standard CMOS. Each cell is a current-mode leaky integrator with a built-in ReLU; each connection is two transistors whose signed strength is a ratio of bias currents. The equilibrium of the network is the solution to a convex program, and latching the cells that are off will hardware linearise the circuit, making its second run exactly linear. Transistor-level SKY130 simulations show that the second run gives the gradient within 1.9%; that hardware linearisation permits large, noise-robust error signals; that a 13-cell network learns the Iris data set; and that learning in situ restores mismatched circuits on which software-trained weights fail, from 53-63% to 88-96% test accuracy.
