Extension of the strain energy updating technique to a multilayered shell model with adaptive

XTLS: Scalable TLS Offloading through Host-SmartNIC Stack Co-Design

XTLS (eXtract TLS), a TLS offloading architecture that liberates the host CPU from this "TLS tax", is presented, a dual-stack design that offloads the entire TLS stack to the NIC—leaving the host to focus on application logic—and an adaptive per-flow symmetric-crypto NIC offload policy that jointly optimizes Requests P...

IBTpoline: Flexible, Robust, and Intel IBT-compliant System Call Hooking

PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration

NVIDIA's Grace Hopper (GH200) superchip represents a new generation of heterogeneous computing, tightly integrating a 72-core Arm-based CPU with a Hopper GPU on a single module via a high-bandwidth, cache-coherent interconnect. By eliminating the conventional PCIe bottleneck for CPU-GPU data movement, this design estab...

ShareMMU: Supporting Secure Address Translation Sharing among Untrusted Accelerators

A Harmony of Ice and Fire: Mitigating Cold Last-Level Cache Effects in Serverless Computing on Commodity Hardware

HostPIMSim: A High-Productivity Framework for Host-Side Processing-in-Memory Simulation

Results show that standardizing the host-interface layer reduces both the engineering cost of PIM simulator development and the energy overhead of simulation-driven workload evaluation, while reducing host CPU utilization and package energy by up to 50% on transfer-intensive workloads.