DiffPower translates design netlists into a PDK-agnostic bytecode representation, enabling analytical gradient computation via reverse-mode automatic differentiation, achieving up to a speedup over single-threaded CPU propagation on the largest evaluated design, with the GPU advantage growing with design scale.
Abstract
Accurate and scalable switching power analysis remains a critical bottleneck in modern physical design, often forcing a trade-off between computational speed and modeling fidelity. We present DiffPower, a GPU-accelerated framework for differentiable power analysis and optimization. DiffPower translates design netlists into a PDK-agnostic bytecode representation, enabling analytical gradient computation via reverse-mode automatic differentiation, achieving up to a $1{,}002\times$ speedup over single-threaded CPU propagation on the largest evaluated design, with the GPU advantage growing with design scale. A hybrid propagation methodology fusing analytical modeling with parallel simulation achieves a median toggle-rate correlation of $r{=}0.96$ across ten industrial and benchmark designs. The resulting \emph{power gradients}, computed up to $904\times$ faster than CPU finite-difference methods with near-perfect rank agreement, enable two downstream applications: (1) gradient-weighted cell sizing, which achieves up to $2.98\times$ improvement over local-power heuristics on industrial designs, with even stronger advantages at the 117K-cell scale where competing methods plateau; and (2) power virus generation via gradient ascent, which yields up to $2.13\times$ higher transition-weighted power, replacing a search process that traditionally requires hours.
This review synthesizes research on graphics processing unit (GPU)-accelerated finite-difference numerical simulation (FDNS) from 2003 to 2025 to clarify how GPU computing has reshaped simulation workflows rather than merely accelerating isolated numerical kernels and to address challenges related to comparability, verification, communication, and reporting in production-oriented FDNS. It combines a Web of Science bibliometric corpus with structured extraction from representative studies reporting performance, scale, precision, accuracy, and implementation characteristics, and organizes the evidence into a four-phase evolution model: graphics-era prototyping, Compute Unified Device Architecture and Open Computing Language expansion and early multi-GPU deployment, systematic optimization, and exascale-adjacent maturity. The synthesis shows that problem scales have grown from roughly one-million-cell demonstrations to multi-GPU and cluster-scale workloads approaching 10 billion unknowns, while precision practice has shifted from single or reduced precision toward double-precision production runs and selectively validated mixed precision; identifies three workload profiles—bandwidth-bound local stencil time stepping, stencil pipelines coupled to global operators, and adaptive or heterogeneous workflows; derives six design rules for memory locality, single-instruction multiple-thread regularity, compute–communication overlap, adaptive work distribution, precision-aware verification, and workflow-level energy and input/output reporting; proposes a minimal metrics card covering the hardware/software stack, baseline, timing scope, precision policy, accuracy evidence, throughput, energy, and input/output inclusion; and outlines a staged modernization blueprint for legacy FDNS solvers. The review concludes that GPU-accelerated FDNS is now an end-to-end workflow problem requiring optimized stencil kernels, explicit numerical verification, transparent reporting, communication-aware orchestration, and reproducible treatment of precision, energy, and storage costs.
The high-performance computing industry is moving beyond an era in which each generation of GPU provides uniform performance gains across all applications. The growing importance of AI is driving GPU architecture towards greater specialization, with more silicon devoted to Tensor Cores and reduced-precision arithmetic. As a result, the benefits of new chip generations are increasingly dependent on the characteristics and computational demands of the workload being run. This project analyzes how the architectural changes introduced across NVIDIA’s Volta, Ampere, and Hopper GPU generations translate into real-world performance and energy efficiency gains.
Experiments were conducted using one GPU per run to isolate device-level performance and avoid the effects of inter-GPU communication. The application suite included scientific computing, AI training, AI inference, and targeted microbenchmarks to stress different parts of the GPU such as matrix computation, memory bandwidth, and data movement. For each workload, we measured performance, execution time, energy consumption, and GPU hardware counters to compare application scaling with the architectural advancements introduced across each generation.
The results show that performance improvements from Volta to Hopper range from 2.95x to 8.32x, demonstrating that generational gains depend strongly on workload characteristics. Matrix-heavy applications, including many modern AI workloads, achieved the largest improvements in both performance and energy efficiency by effectively using increasingly capable Tensor Core hardware. In contrast, memory-bound and vector-based workloads experienced more modest gains because memory bandwidth and general-purpose compute resources have scaled more slowly.
Overall, the results show that specialization can deliver substantial performance and efficiency gains, but only when workloads can effectively use the hardware being added. Future work will extend the analysis to additional GPU generations and applications, while exploring frequency capping and more detailed die-area analysis.
Supervisor: Ian Karlin
Matthew Tindale, I. Karlin, Tobias Salamon et al.· Inquiry@Queen's Undergraduat...· 0 citations
FSZ, a GPU error-bounded lossy compressor that redesigns the prediction stage with three mutually reinforcing algorithmic innovations to achieve both higher compression ratios and higher throughput within a single CUDA kernel, achieves the highest average throughput among all evaluated compressors.
The lattice Boltzmann method (LBM) is a well-established approach for simulating fluid flows at the mesoscopic scale. With the stagnation of Moore's law, high-performance computing has shifted toward GPU accelerators, necessitating programming models that ensure both portability and efficiency across diverse hardware platforms. We present PortLBM, an extensible portable LBM framework built on SYCL that integrates cross-platform GPU support with interactive real-time visualization. PortLBM supports diverse simulation scenarios ranging from K\'arm\'an vortex streets and wing flows to porous media, and is designed for easy extension with new algorithms and backends. As part of a performance portability study, we evaluate PortLBM on contemporary GPU architectures from NVIDIA, AMD, and Intel, examining the impact of three data layouts (stream, bundle, and collision) and four algorithmic variants on simulation throughput. Our results show that no single configuration achieves optimal performance across all GPU vendors, confirming the need for system-specific tuning. The stream layout maximizes bandwidth and performs best on the contemporary NVIDIA and Intel GPUs, while the bundle layout improves cache efficiency and excels on the AMD GPU. Two-lattice schemes achieve higher throughput while one-lattice schemes are preferable under memory constraints. Our work underscores the necessity for adaptable, portable LBM software in increasingly heterogeneous computing environments.
Alexander Strack, Marcel Graf, Alexander Van Craen et al.· arXiv.org· 0 citations
Power analysis is crucial in modern chip design flow. Particularly, time-based power analysis can provide fine-grained power consumption information to facilitate the diagnosis of power issues and guide power optimization accordingly. However, it may take tens of hours to conduct time-based power analysis on modern large-scale circuits, which greatly slows down the power optimization flow. In this paper, we present the first GPU-accelerated gate-level time-based power analysis framework. We propose a novel data structure to enable efficient state-dependent power retrieval. To accommodate the imbalanced event distribution across gates, we propose an event-density-aware partitioning strategy that allocates GPU threads based on gate event density. Finally, we fuse the power computation into a single kernel invocation to reduce redundant work in separate kernels. Experimental results show that our proposed framework achieves high accuracy while delivering up to 37.63x end-to-end speedup compared to multi-threaded Synopsys PrimeTime PX.
Wei-Hao Wang, Yi-Kang Ouyang, Hong-Yuan Liu et al.· 0 citations
Error-bounded lossy compression is essential for storing and transferring the vector-field data produced by large-scale scientific simulations. Although it enforces a user-specified error bound to limit numerical distortion, it does not preserve the field's topology: small admissible perturbations can create or eliminate critical points on which downstream feature analysis depends. Existing GPU compressors achieve high throughput but are topology-agnostic, whereas the only compressor with provable critical-point preservation (cpSZ) runs on the CPU at throughput far below the data-generation rates of modern GPU-based systems. We observe that, although preserving critical points is inherently a coupled and sequential constraint, it can be reformulated into independent parallel tasks, either on a per-block basis or, speculatively, on a per-point basis. We present FaCTz, the first GPU-based error-bounded lossy compressor that guarantees critical-point preservation. FaCTz provides a block-wise mode optimized for throughput and a speculative per-point mode optimized for compression ratio. Across three vector-field datasets, FaCTz preserves every critical point while achieving throughput of up to 60 GB/s, approximately two orders of magnitude (up to approximately 640x) faster than the multithreaded CPU implementation of cpSZ. Its speculative mode further improves the compression ratio by approximately a factor of two over the throughput-oriented mode.
Mingze Xia, Yuxiao Li, Sheng Di et al.· 0 citations
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