An adaptive congestion-aware graph neural routing framework with hybrid microcoded event-driven control for network-on-chip systems

Abstract

Network-on-Chip (NoC) architectures have become a fundamental communication backbone for many-core processors, artificial intelligence accelerators, edge-computing platforms, and high-performance embedded systems. However, achieving efficient packet routing in large-scale NoCs remains challenging due to dynamic traffic variations, congestion propagation, limited global network visibility, and stringent hardware constraints. Conventional deterministic and heuristic routing algorithms suffer from reduced adaptability under non-uniform traffic conditions, whereas existing deep reinforcement learning (DRL)-based routers primarily rely on local state representations and finite-state-machine (FSM) controllers, limiting their scalability, topology awareness, and hardware deployability. To address these limitations, this work proposes an Adaptive Congestion-Aware Graph Neural Routing Framework with Hybrid Microcoded Event-Driven Control for Network-on-Chip Systems. The proposed framework integrates three complementary components: (i) an Adaptive Congestion-Aware Graph Neural Network (ACA-GNN) encoder that generates compact topology-aware embeddings by capturing local and multi-hop congestion dependencies through congestion-aware message propagation, (ii) a quantized Deep Reinforcement Learning (DRL) agent that performs low-latency adaptive routing decisions using compact graph embeddings, and (iii) a Hybrid Microcoded Event-Driven Controller (H-µEDC) that replaces conventional FSM-based control with programmable event-triggered micro-routines to ensure deterministic routing execution. The proposed architecture is implemented on a Xilinx Zynq-7000 FPGA and evaluated using BookSim2 cycle-accurate simulation, Orion 3.0 power modeling, synthetic traffic patterns, and PARSEC/Rodinia benchmark workloads. Experimental results demonstrate up to 48% lower packet latency, and 31% lower energy per flit compared with state-of-the-art heuristic and machine-learning-based routing approaches. Hardware implementation further requires only 1.2% LUTs, 1.4% flip-flops, three DSP blocks, one BRAM, and 0.556 W power consumption while maintaining deterministic single-cycle routing decisions using cached ACA-GNN embeddings. These results demonstrate that the proposed ACA-GNN-HµEDC framework effectively combines topology-aware routing intelligence, congestion adaptivity, hardware efficiency, and scalability, making it a practical solution for next-generation many-core Network-on-Chip systems.