Reliable HCI-Based Programming in V-NAND Flash Memory: Co-optimization of SWL Waveform and Trap-Cut Architecture

Abstract

Hot carrier injection (HCI)-based programming has emerged as a high-efficiency alternative to conventional Fowler–Nordheim (FN) tunneling for next-generation vertical NAND (V-NAND), yet its practical implementation is severely constrained by coupled physical reliability trade-offs: program disturb, Z-interference, and retention degradation. This study investigates these bottlenecks through technology computer-aided design (TCAD) simulations calibrated to experimental PN junction and V-NAND reference data, and proposes a co-optimization framework combining switch word-line (SWL) waveform engineering with a trap-cut storage-node architecture. We demonstrate that the severe program disturb observed during the hold phase originates from localized lateral electric field crowding and subsequent impact ionization. This can be electrostatically mitigated by applying the negative SWL bias only during the set-up phase and returning the SWL to 0 V during the hold phase, achieving a 46.3% reduction in disturb under the most stringent victim-state conditions. Furthermore, we show that the aggravated Z-interference and lateral charge migration stem from the spatial spreading of hot electrons into the continuous spacer charge trap layer beyond the gate boundaries. By implementing a physically segmented trap-cut structure, the lateral charge transport path is severed, eliminating spacer charge trapping and yielding a 37.3% improvement in Z-interference over the conventional FN baseline while improving long-term retention. The proposed approach decouples the performance-reliability trade-offs and provides physical insight and an architectural solution for high-density V-NAND scaling. Experimental validation of the proposed scheme is a subject for future work.