An Edge On-Chip-Learning Convolutional Spiking Neural Network Processor Based on Error Backpropagation via Spatiotemporal Nodes of Spike Events.

Abstract

While Spiking Neural Networks (SNNs) offer high energy efficiency for edge computing, implementing on-chip backpropagation for convolutional topologies remains challenging due to substantial memory and logic overhead. Existing hardware mostly relies on offline training or local heuristic rules, which limits feature extraction in complex tasks. This paper presents a convolutional SNN processor featuring ConvTempo, an end-to-end global optimization framework. By restricting each neuron to fire at most once, the algorithm executes surrogate-gradient backpropagation sparsely at maximum membrane potential nodes, minimizing gradient computation. Simultaneously, a dedicated Output Channel- First (OC-First) scheduling mechanism reduces the membrane-potential-related intermediate state storage to O(N), while the Time-Channel Indexed cache reduces the AER storage overhead through compact spike-event encoding. Prototyped on a Xilinx Zynq-7045 FPGA at 100 MHz, the processor utilizes merely 8 DSPs alongside 94.5 Block RAMs (BRAMs) while consuming 0.589 W. Compared with an STDP-based baseline using the same lightweight convolutional topology, this work achieves absolute accuracy improvements of 0.64%, 1.29%, and 2.69% on MNIST, Fashion-MNIST, and ETH-80, respectively. Despite the implementation of chain-rule-based global surrogate-gradient backpropagation, the logic resource utilization remains competitive with lightweight shallow-topology designs, providing a high-accuracy on-chip learning solution for resource-constrained edge applications.