An Analog Frequency-Domain Systolic Array for Energy-Efficient AI Acceleration at the Edge

Abstract

The increasing computational demands of artificial intelligence (AI) inference at the edge require hardware accelerators capable of overcoming the von Neumann bottleneck while operating under power constraints. Conventional digital architectures based on multiply–accumulate (MAC) units are limited in energy efficiency and scalability for resource-constrained applications. This work presents a proof-of-concept AI accelerator based on analog frequency–domain computation implemented within a semi-systolic array architecture. The proposed approach exploits frequency mixing to perform multiplication and accumulation operations in hardware, enabling the execution of matrix–matrix operations, which constitute the General Matrix Multiplication (GEMM) methods that dominate the computational workload of convolutional and fully connected neural networks. The proposed system consists of a custom printed circuit board controlled by an ATmega328P microcontroller(Microchip Technology Inc., Chandler, AZ, USA) and a software stack designed to interface with standard machine learning frameworks such as PyTorch. The software layer enables neural network operations, including convolutional and fully connected layers, to be mapped onto hardware-executed matrix–matrix computations through an abstraction analogous to the General Matrix Multiplication (GEMM) functionality provided by Level-3 Basic Linear Algebra Subprograms (BLAS). Matrix multiplication and accumulation are partly performed directly by the hardware processing elements, while the software control unit coordinates data movement and computation scheduling. Although bias operations are not implemented in the current prototype, their comparatively low computational cost makes them less critical to the overall acceleration strategy. A quantization-aware mapping methodology constrained by analog-to-digital and digital-to-analog converter specifications is introduced to translate neural network operations into frequency–domain computations. The paper further describes the hardware architecture, communication protocols, software stack organization, and interactions between system components. In addition, the effects of analog nonidealities and error sources associated with frequency–domain multiplication are investigated, and simulations of the proposed processing elements are presented to evaluate the computational approach. Experimental and simulation results demonstrate the feasibility of performing dense linear algebra operations through analog frequency–domain processing and validate the operation of the processing elements. The study further explores converter resolution, frequency interference, and analog component nonidealities and provides a comparison with conventional digital and other low-power accelerator approaches. The results indicate that exploiting the inherent parallelism of analog computation offers a promising pathway toward ultra-low-power AI inference, making the proposed architecture a potential alternative for energy-constrained edge applications.