REF-CIM: A 40-nm Non-Ideality Tolerant and Energy Efficient RRAM Compute-in-Memory Macro With Configurable Precision for Edge AI

Abstract

Compute-in-Memory (CIM) based on resistive random access memory (RRAM) offers significant advantages in energy efficiency and parallelism, making it a promising solution for accelerating neural networks. However, the computational accuracy, energy efficiency, and flexibility of current CIM chips are still challenged by practical issues such as device and circuit-level non-ideality and the high overhead of peripheral circuits, which remain inadequately addressed in existing designs. To address these challenges, this work proposes REF-CIM, a 40nm robust, energy efficient and flexible RRAM- CIM macro that achieves non-ideality tolerance, high energy efficiency and configurable precision, featuring: 1) a complementary multi-bit input unit (CMIU) with symmetric bit-line access; 2) a proportional current-scaling clamp circuit (PCSC); 3) a distributed tree-based sparse analog-to-digital converter (DTS-ADC); and 4) a configurable multi-mode deployment scheme for supporting diverse neural network precisions. The performance of the proposed macro is evaluated through chip measurements, considering non-ideal effects such as IR-drop, device variation, and analog circuit noise. Simulation results calibrated with measurement data demonstrate a peak energy efficiency of 29.1 TOPS/W@8bIN/8bW/16bOUT, with classification accuracy reaching 92% on the CIFAR-10 dataset under 10% device variation.