Automated PLC Programming Using a Multi-Task LLM System

StarVerus: LLM-Powered Multi-Agent Collaboration for Industrial Rust Code Verification Automation

Creating code specifications is a crucial measure to improve the trustworthiness of many industrial systems implemented in Rust with high security requirements. Because writing specifications requires highly specialized professionals and is time-consuming, the automatic generation of specifications, enabled by large language models (LLMs), has received increasing attention and shown promising results. However, these methods typically focus on partial specification generation (generating proofs after the contract is known) and on extracting dependencies between code modules using predefined relations. This is not suitable for real-world industrial systems where the goal is to generate complete specifications from scratch and where the complex dependencies between code modules are variable. To address this, we propose a multi-agent collaborative framework, StarVerus, to automate the verification of industrial Rust code. Specifically, StarVerus addresses the aforementioned limitations in two ways: 1) In the generation phase, it instructs the LLM to generate all specifications for a given code, and in the repair phase, it uses a cascaded two-stage process of contract alignment and proof repair to correct them; 2) In both the generation and repair phases, it utilizes a function call graph to adaptively obtain bidirectional contextual information (i.e., what it calls and what calls it) for each code module as an additional information source for the LLM. Furthermore, StarVerus introduces a planner-repairer-actor-rewriter multi-agent paradigm to further enhance the proof repair capabilities. Finally, the effectiveness of StarVerus is validated through experiments on benchmark datasets and deployment in a real operating system.

PLCBench: Can Autonomous LLM Agents Turn PLC Access into Sustained Physical Impact?

PLCBENCH is presented, to the authors' knowledge, the first real-PLC hardware-in-the-loop (HIL) framework for characterizing this cyber-to-physical capability and its boundaries and it combines vendor-native interaction, commercial PLC execution, closed-loop reduced-order process simulation, and independent outcome verification.

SemaPLC: A Project-Grounded, Verification-Gated Agent Harness for PLC Code Generation

Programmable logic controllers (PLCs) run industrial plants, and large language models can already generate independent program organization units (POUs) for them. Whether such logic integrates into an existing PLC project and then runs correctly has been checked only in limited tests. We present \textsc{SemaPLC}, a project-grounded and verification-gated agent harness assembled from conventional tools but governed by a strict completion rule. Rather than stopping when the model judges its own output adequate, \textsc{SemaPLC} declares a task complete only when logged external checks confirm it. Those checks cover the specification, the compilation, and the behavior on a live runtime. On 117 independent-POU tasks matching existing benchmarks, it attains the highest strict verified pass rate on all seven models (72.6\% mean). On a project-context track of 65 tasks whose generated logic must compile and run inside a real project, it attains the highest mean on integrated compilation, static behavior, and dynamic behavior. Of the three layers, dynamic behavior is the most revealing. We measure it by deploying the generated and the reference logic to a live PLC runtime and comparing their executed traces. All methods fall within 10 static points of one another, whereas dynamic scores separate them sharply, from 22.4 to 31.4 for the baselines against 52.2 for \textsc{SemaPLC}. Overall, our verification-gated harness raises the mean at every layer and most sharply at runtime. Execution, not static scoring, is the faithful test of whether generated control logic actually works. \textsc{SemaPLC} is open-sourced at https://github.com/midea-ai/SemaPLC.

VTR-LLM: Multi-Agent LLM Framework for Automated Debugging of FPGA CAD Flows

Modern FPGA computer-aided design (CAD) flows have grown increasingly complex, integrating numerous stages, configuration parameters, timing constraints, and physical implementation specifications. As designs scale, failures often arise from subtle interactions across command-line options and constraint files, making debugging time-consuming and heavily dependent on expert knowledge. Identifying the root cause of such failures and determining the appropriate corrective action remains a major productivity bottleneck in CAD workflows. This paper presents VTR-LLM, a fully automated, multi-agent framework for diagnosing and resolving failures in the Verilog-to-Routing (VTR) CAD flow. VTR-LLM leverages large language models (LLMs) in combination with retrieval-augmented generation (RAG) and specialized agents that target distinct sources of errors, including command-line invocations, timing constraints (i.e., Synopsys Design Constraints or SDC), and floorplanning specifications. A Classification Agent dynamically assigns each failure to the most appropriate agent and supports sequential resolution for compound failures involving multiple error sources. The system leverages LLMs without requiring fine-tuning, enabling use of the latest models such as GPT-OSS-120B, by using RAG and intelligent agents to add domain-specific context and behaviours. We evaluate VTR-LLM using a dataset of 92 distinct VTR failure cases spanning multiple error patterns and levels of complexity. VTR-LLM can resolve 95% of all failures fully automatically, with robust performance across error categories. Additional studies demonstrate the impact of documentation retrieval scope, tool iteration, and LLM model choice on resolution accuracy and inference cost.

Evaluating LLMs in ROS robotic software code generation

Integrating High-Level Requirements to Low-Level Tests with Machine-Readable V&V Specifications

Modern software teams have mature tools for low-level testing, such as pytest, JUnit, and Jest, which make it inexpensive to write unit tests and run them on every commit. Systems engineering, in parallel, has developed rigorous principles for design verification and validation (V&V), which has worked very well across engineering discipline to align user expecations and requirements with developers'deliverables. In practice, however, the two rarely connect, and the link between users'high-level requirements and the low-level tests that machines actually run is maintained by hand, if at all. This gap is increasingly costly for AI-enabled and cyber-physical systems, for which regulators now ask for traceable evidence that high-level requirements are met, while raw test results provide little of the structure such evidence requires. We introduce VNVSpec, an open-source framework that makes V&V specifications machine-readable and executable. With this framework, users state high-level requirements directly or import them from catalogs derived from published standards. Then, the framework checks requirement quality, supports decomposition into module-level requirements with explicit metrics and acceptance criteria, links these requirements to test results through a traceability graph, and compiles the collected evidence into verdicts and audit-ready reports. We evaluate the framework by self-application, in which it is continuously assessed in CI against its own specification of 36 requirements verified by 449 tests, completed within limited time which scales linearly and thus can handle up to 10,000 requirements. We also discuss how the framework extends to testing black-box AI models and AI coding agents. The framework, its full test suite, the catalogs, and the benchmark scripts are available at https://github.com/ai-vnv/vnvspec.