It is shown cut-count minimization is an unreliable proxy in practice: a globally cleaner partition can reduce cross-cut count yet increase wall-clock time, because it imbalances T-gate density across halves and inflates per-half stabilizer-frame size.
Abstract
We present an exact amplitude simulator for Clifford+T quantum circuits that combines a Feynman path sum across a balanced qubit bipartition with stabilizer-frame simulation on each half. The construction extends prior stabilizer-based Schr\"odinger-Feynman methods in three directions: recursive multilevel bipartition into a binary tree, automatic fallback to dense state-vector simulation when a leaf's stabilizer frame would exceed its memory ceiling, and a cost-model-driven partition selector that replaces the standard cut-count minimization heuristic. We show cut-count minimization is an unreliable proxy in practice: a globally cleaner partition can reduce cross-cut count yet increase wall-clock time, because it imbalances T-gate density across halves and inflates per-half stabilizer-frame size. Our cost model substitutes the stabilizer-frame bound 2w for the dense 2n ceiling per side and explicitly models per-amplitude readout cost; isolating that term uncovered a quadratic-asymptotic inefficiency in the leaf simulator's end-of-path amplitude extraction, fixed by replacing it with an existing O(F * s * n) single-amplitude inner product. On a structured hierarchical n=16 benchmark the recursive simulator beats monolithic stabilizer-frame simulation by 92x to 17,645x, wins by 79x per path against a dense half-state-vector baseline under an identical cut, and beats a production state-vector simulator end to end by up to 47.9x (median ~5x). On adversarial random Clifford+T circuits the dense state vector wins past a crossover near n/2 cross-cut gates -- the regime the cost model identifies. The dominant cost, the cross-cut Feynman sum, is embarrassingly parallel with constant inter-worker communication, unlike recent matrix-product-state stabilizer-tensor methods whose inner contraction loop is sequential.
Fault-tolerant protocols often consist largely of stabilizer subcircuits, yet the non-Clifford operations required for universality make exact sampling costly. We present SymFT, a high-throughput simulator for Clifford-dominated circuits with Pauli rotations, stochastic Pauli noise, mid-circuit Pauli measurements, and measurement-record-controlled Pauli feedback. It combines two ideas. First, symbolic Clifford--Pauli frame factorization reduces branch-probability sampling to Pauli rotations and measurement projectors, with noise and feedback represented by symbolic signs. Since the residual Clifford and Pauli frames are unitary, they do not affect branch probabilities and need not be applied in every shot. Second, adaptive stabilizer-coordinate planning uses a shared stabilizer--destabilizer tableau to define the basis and stores only the active non-stabilizer degrees of freedom in a dynamically sized dense active-state vector. It resolves basis changes once and emits direct multi-coordinate sampling instructions, thereby avoiding per-shot tableau updates and localization-induced Clifford transformations of the dense vector. Across the tested pure-Clifford and near-Clifford circuits, SymFT achieves state-of-the-art sampling performance. On a single CPU core, it achieves a $2.51\text{--}2.56\times$ speedup over Stim for surface-code circuits and a $1.86\text{--}3.51\times$ speedup over Clifft for magic-state cultivation and distillation circuits. For the tested cultivation circuits, its GPU sampling throughput also exceeds that of our previous simulator, SOFT, by more than two orders of magnitude.
Fault-tolerant architectures implement non-Clifford T gates through magic-state distillation, so the T-count of a synthesized circuit dominates its physical cost. The Solovay-Kitaev algorithm approximates any single-qubit unitary from a finite gate set with a sequence length that grows only polylogarithmically in the inverse target error, but it optimizes for numerical convergence rather than circuit economy, and its output carries structural redundancy that a gate-level compiler cannot see. We report a measurement of what diagrammatic post-processing recovers from that redundancy. Twelve hundred random single-qubit targets, spanning the three Pauli rotation families and the general gate U(theta, phi, lambda), are synthesized over Clifford+T at three recursion depths, translated into graph-like ZX-diagrams, simplified by automated rewriting, and extracted back to circuits. Post-processing removes 26.6-30.1% of the total gate count and 18.5-22.2% of the T-count. The absolute saving grows with recursion depth, from about 60 to about 1600 gates, while the fractional saving does not: it rises slightly from the shallowest setting and is then flat across a twenty-five-fold change in circuit length, and by the deepest setting the four target families are no longer distinguishable from one another. Because the rewrite rules preserve the implemented linear map, the approximation error is unchanged. The compile-time cost of the rewriting layer, by contrast, grows sharply with depth and comes to dominate the synthesis itself.
Dulari De Silva, Anuradha Mahasinghe, Chon‐Fai Kam et al.· 0 citations
The contrast between settings is the central finding: when approximate outputs can be rescued by post-processing, the transformer succeeds; when exact discrete correctness is required, autoregressive drift limits reliability, with both inference-time search and data scaling as effective levers while training-side fine-tuning and model-level diversification are not.
Noisy intermediate-scale quantum computers are constrained by circuit depth, while product-formula simulation of spin systems leads to narrow and deep circuits. Here we introduce a fan-out-based gadget compiler that trades circuit depth for width in simulations of Heisenberg-type nuclear magnetic resonance (NMR) Hamiltonians. Each logical spin is encoded into a small repetition-code register sized by its interaction degree, so that all pairwise interactions of a given Pauli type execute in parallel after a logarithmic-depth CNOT fan-out, and the redundant registers provide error detection for post-selection at no additional algorithmic overhead. The central result is a fixed-protocol resource comparison of the two compilations, transpiled to heavy-hex superconducting and all-to-all trapped-ion targets across a set of NMR spin systems. For interaction graphs with a high-degree hub the volume-optimal schedule halves the two-qubit depth and reduces the volume 1.7-fold for the 13-spin demonstration, which on heavy-hex also lowers the two-qubit gate count, and the depth reduction rises to 2.5-fold on all-to-all for the highest-degree molecule studied. On all-to-all the two-qubit gate count rises for every system, so the volume reduction is a benefit on depth-limited hardware. The gain grows with the degree inhomogeneity of the interaction graph and vanishes for dense uniform graphs, where the optimum is the sequential circuit. We simulate the zero-field NMR spectrum of tetramethylsilane, a 13-spin star system. Under a noise model scaled from a published present-day processor calibration, the shallower gadget circuits match or surpass the sequential compilation only after post-selection on their built-in error detection, once error rates improve by one to one and a half orders of magnitude. We verify the spectra against an independent classical computation.
Efficient simulation of large-scale quantum circuits remains a critical bottleneck in quantum computing research, as the exponential memory and runtime growth of state vector-based approaches limits scalability beyond tens of qubits. This paper presents a scalable quantum circuit simulation that extends the conventional stabilizer tableau formalism to support mixed Clifford and non-Clifford operations on multi-GPU platforms. The proposed quantum simulation introduces a dynamically extensible tableau representation that eliminates destabilizer redundancy and distributes independent Pauli groups across GPUs for fine-grained parallelism. A two-stage CUDA kernel pipeline efficiently manages the branching and merging of tableau rows during non-Clifford evolution by separating counting required rows from row updates, ensuring deterministic updates and compact memory usage. Comprehensive evaluations on 128 circuits from QASMBench demonstrate that the proposed simulation achieves 78.1% overall coverage, executing many non-Clifford circuits that other simulators failed to complete. Compared with state vector-based frameworks, our simulation reduces peak memory consumption by up to 10126 × and maintains stable multi-GPU scalability, successfully executing circuits up to 30000 qubits.
Hyunjoon Shin, Seokhyeon Lee, Myeongjin Kwak et al.· International Conference on...· 1 citation· ⚡1
Logical entangling gates are a major source of physical spacetime overhead in fault-tolerant quantum computation. Phantom codes reduce this cost by implementing every ordered in-block logical CNOT through physical qubit permutations and Pauli-frame updates. Whether this mechanism can coexist with the low-weight stabilizer structure of qLDPC codes is a central question for low-overhead fault-tolerant architectures. We give a deterministic answer within binary CSS hypergraph product (HGP) codes. Up to natural equivalences, the simplex-repetition family is the unique HGP family satisfying the phantom condition. We then evaluate this family under circuit-level noise in logical GHZ-state preparation and Trotterized many-body quantum simulation. The codes retain low-weight stabilizer checks and yield concrete advantages over rotated surface-code baselines in both benchmarks. Reconfigurable neutral-atom arrays offer a natural setting for this approach, supporting nonlocal qLDPC operations while enabling in-block logical CNOTs without additional physical operations. Together, these results make precise how permutation-based logical entangling constrains code design within the HGP framework, demonstrate the circuit-level benefits of the unique family, and guide the search for phantom qLDPC families with better asymptotic parameters for low-overhead fault tolerance on neutral-atom hardware.